Breakdown of UltraSPARC Processors

What are UltraSPARC Processors?

Simply put, UltraSPARC processors are a family of microprocessors developed by Sun Microsystems based on the SPARC V9 architecture. It is an example of RISC (Reduced Instruction Set Computer).

This was a leap from 32-bit to 64-bit computing, which allows servers to handle complex operations. As a result, UltraSPARC could perform complex operations faster.

These processors have served Sun Microsystems for years to provide high-performance computing solutions. They had their place on servers, workstations, and legacy applications.

Understanding the UltraSPARC Architecture

As already mentioned, UltraSPARC is an example of RISC architecture that aims to simplify processing. Here are the salient features of this architecture:

Memory: UltraSPARC architecture consists of 8-bit bytes of memory. There are two consecutive bytes in a halfword. Words consist of four bytes, and doublewords consist of eight bytes. Programs running on UltraSPARC utilize the Virtual Address Space (264 bytes). The virtual address space is split into pages. These pages are stored in two ways, either in physical memory or on the disk.

Registers: It has a large register file comprising more than 100 general-purpose registers. However, each procedure can access only 32 registers at once. The SPARC hardware uses a register window to manage operations for different procedures. It also uses a Program Counter, a code register, and other control registers.

Data Formats: Binary numbers are used to represent integers with sizes of 8-, 16-, 32-, or 64-bits. Characters are encoded using 8-bit ASCII values. Floating-point numbers are stored in one of three formats:

• single-precision
• double-precision
• or quad-precision.

Instruction Formats: Similar to SPARC, its architecture uses three primary instruction formats. All the instructions are 32 bits long, with the first two bits identifying the format.

• Format 1: Used for call instructions
• Format 2: Used for branch instructions
• Format 3: Used for all other instructions, such as register load and store

Now that you know the architecture, let’s look at the key architectures of the UltraSPARC series.

UltraSPARC II

• Blackbird” was the code name for UltraSPARC II
• A total of 5.4 million transistors were contained on the die
• L2 cache capacity ranged from 1 to 4 MB
• Supports multimedia with Visual Instruction Set (VIS)
• Directly connects to four processors with minimal latency
• Implements snooping-based cache coherency
• Includes two dedicated graphics execution units
• 16 KB instruction cache with single-cycle branch prediction
• Incorporates power management features
• Supports software-controlled prefetch instructions
• Capable of handling multiple outstanding requests simultaneously
• In 1999, it was ported to a 0.25 mm process
• Four derivatives of this processor are UltraSPARC IIi, UltraSPARC IIe, UltraSPARC IIe+, and Gemini
• Interestingly, Gemini was Sun Microsystems’s first attempt to produce a multithreaded processor

UltraSPARC III

UltraSPARC III is an in-order superscalar microprocessor, meaning it responds to instructions in the order they are received and can issue multiple instructions per clock cycle.

It features an integrated memory controller and a dedicated multiprocessor bus to provide shared memory multiprocessing performance.

Additionally, it has the following noteworthy aspects:

• Its codename was “Cheetah”
• Its main architect was Gary Lauterbach
• Approximately 75% of transistors are located in tags and caches
• Further development: UltraSPARC III Cu, UltraSPARC IIIi, and UltraSPARC IIIi+

UltraSPARC IV

As part of the fourth generation of UltraSPARC microprocessors, it was the first multi-core SPARC processor. Sun’s Throughput Computing initiative led to the development of UltraSPARC IV.

Let’s take a look at the key characteristics of UltraSPARC IV:

Dual-core architecture: Features two UltraSPARC III-derived processor cores on a single chip.

Built in 0.13 µm CMOS: Fabricated using advanced technology with a clock frequency of 1.2 GHz.

Large cache system:

• Data Cache Unit (DCU): 64 KB 4-way set associative L1 data cache with 2 KB write and pre-fetch caches.
• Instruction Issue Unit (IIU): Contains a 32 KB 4-way set associative instruction cache and instruction TLB.

Cache operation:

• L1 caches operate at half speed, with 2-cycle loads and stores.
• Independent pre-fetch cache can load data as needed.
• Write cache defers writes to the L2 cache, improving bandwidth.

Integer Execute Unit (IEU): Includes two add/logical units, a branch unit, and supports pipelined integer adds and multiplies.

Floating-Point Unit (FPU):

• Two pipelined units for addition and multiplication
• A non-pipelined unit for division and square root computation (20-25 cycles)
• Enhanced IEEE 754 error handling for floating-point operations
• Graphics hardware sharing the adder and multiplier

L2 Cache: 2×8 MB L2 cache, with 128 B cache lines (down from 512 B in UltraSPARC III) to reduce contention.

Memory Control Unit (MCU): On-chip MCU and the L2 cache controller to reduce latency.

Chip Multithreading (CMT): Each core executes one thread, a different form of multi-threading compared to traditional implementations.

Multi-processing support: Snoop controller ensures cache coherency across multi-processor systems.

Theoretical peak performance: 2.4 Gflop/s at 1.2 GHz.

Future scaling: Potential for frequency scaling in later stages of its lifecycle.

Chip Layout and Design: The Memory Control Unit and L2 cache controller are integrated into the chip to minimize latency.

The Future of Business Applications Running on SPARC Servers

SPARC servers have their place in many organizations. Unfortunately, it’s not due to the uniqueness of the hardware anymore. Rather, it’s because they lack good alternatives for running their mission-critical Solaris applications.

These applications are vital to their business, powering day-to-day operations. But outdated hardware is causing serious issues: downtime, business disruption, security breaches, higher maintenance costs, spare parts scarcity, and a diminishing pool of skilled professionals.

This creates a situation that demands immediate action. Yet, businesses are either not prioritizing or don’t know where to start.

SPARC hardware emulation emerges as a risk-free, quick, and economical alternative here. If you’re looking for the leader in hardware emulation, Stromasys is the way to go.

Charon-SSP is Stromasys’ meticulously engineered SPARC emulator. It replicates the behavior of your current hardware and creates a similar environment on modern hardware, either on-premises or cloud.

As a result, your critical legacy applications run unmodified on modern platforms without rewriting, re-designing, or recertifying. The entire process is frictionless and can be completed within days to weeks.