A Complete UltraSPARC Breakdown: Evolution, Features, and Architecture

What are UltraSPARC Processors?

Simply put, Sun UltraSPARC processors are a family of microprocessors developed by Sun Microsystems based on the SPARC V9 architecture. It is an example of RISC (Reduced Instruction Set Computer).

This was a leap from 32-bit to 64-bit computing, which allows computers to handle complex operations. As a result, UltraSPARC architecture-based servers and workstations could perform operations faster. It was primarily deployed on the Sun4u architecture, a 64-bit platform that used the high-speed UPA interconnect and supported up to 64 CPUs. This marked a major shift from earlier 32-bit designs like Sun4m (SuperSPARC-based, max 4 CPUs with SBus/MBus) and Sun4d (also 32-bit with XDBus support).

These processors have served Sun Microsystems for years to provide high-performance computing solutions. They had their place on servers, workstations, and legacy applications-running systems.

Understanding the UltraSPARC Processor Architecture

As already mentioned, the UltraSPARC processor is an example of RISC architecture that aims to simplify processing. Here are the salient features of this architecture:

Memory: UltraSPARC architecture consists of

• 8-bit bytes of memory (2 successive bytes – halfword, 4 bytes – word, 8 bytes – doublewords)
• Virtual Address Space (264 bytes), split into pages and stored in physical memory or on the disk.

Registers: UltraSPARC processor comprises

• A large register file having more than 100 general-purpose registers
• Only 32 registers accessed at a time
• Register window to manage operations for different procedures
• Control registers like Program Counter, code register, etc.

Data Formats: UltraSPARC processors also use:

• Binary numbers with sizes of 8-, 16-, 32-, or 64-bits to store integers
• 8-bit ASCII values for characters
• Floating-point numbers in 3 formats –

single-precision

double-precision

or quad-precision.

Instruction Formats: UltraSPARC architecture uses:

• 3 primary instruction formats (32 bits long)
• First 2 bits identifying the format as –

Format 1: Used for call instructions

Format 2: Used for branch instructions

Format 3: Used for all other instructions, such as register load and store

Now that you know the basic architecture, let’s look at the key members of the UltraSPARC series.

UltraSPARC II Processor

UltraSPARC II is the first in our series, and it includes a total of 5.4 million transistors contained on the die. L2 cache capacity ranged from 1 to 4 MB. It supports multimedia with Visual Instruction Set (VIS).

It connects directly to four processors with minimal latency. UltraSPARC II implements snooping-based cache coherency. The microprocessor includes two dedicated graphics execution units. It includes 16 KB instruction cache with single-cycle branch prediction.

UltraSPARC II incorporates power management features and supports software-controlled prefetch instructions. It is capable of handling multiple outstanding requests simultaneously.

• “Blackbird” was the code name for UltraSPARC II.
• The chief architect was Marc Tremblay.
• In 1999, it was ported to a 0.25 mm process.
• Four derivatives of this processor are UltraSPARC IIi, UltraSPARC IIe, UltraSPARC IIe+, and Gemini.
• Interestingly, Gemini was Sun Microsystems’s first attempt to produce a multithreaded processor.

UltraSPARC III Processor

UltraSPARC III is an in-order superscalar microprocessor, meaning it responds to instructions in the order they are received and can issue multiple instructions per clock cycle.

It features an integrated memory controller and a dedicated multiprocessor bus to provide shared memory multiprocessing performance.

Additionally, it has the following noteworthy aspects:

• Its codename was “Cheetah”
• Its main architect was Gary Lauterbach
• Approximately 75% of transistors are located in tags and caches
• Further development: UltraSPARC III Cu, UltraSPARC IIIi, and UltraSPARC IIIi+

UltraSPARC IV Processor

As part of the fourth generation of microprocessors in UltraSPARC servers and workstations, it was the first multi-core SPARC processor. Sun’s Throughput Computing initiative led to the development of UltraSPARC IV.

Let’s take a look at the key characteristics of UltraSPARC IV microprocessors:

Dual-core architecture: Features two UltraSPARC III-derived processor cores on a single chip.

Built in 0.13 µm CMOS: Fabricated using advanced technology with a clock frequency of 1.2 GHz.

Large cache system:

• Data Cache Unit (DCU): 64 KB 4-way set associative L1 data cache with 2 KB write and pre-fetch caches.
• Instruction Issue Unit (IIU): Contains a 32 KB 4-way set associative instruction cache and instruction TLB.

Cache operation:

• L1 caches operate at half speed, with 2-cycle loads and stores.
• Independent pre-fetch cache can load data as needed.
• Write cache defers writes to the L2 cache, improving bandwidth.

Integer Execute Unit (IEU): Includes two add/logical units, a branch unit, and supports pipelined integer adds and multiplies.

Floating-Point Unit (FPU):

• Two pipelined units for addition and multiplication
• A non-pipelined unit for division and square root computation (20-25 cycles)
• Enhanced IEEE 754 error handling for floating-point operations
• Graphics hardware sharing the adder and multiplier

L2 Cache: 2×8 MB L2 cache, with 128 B cache lines (down from 512 B in UltraSPARC III) to reduce contention.

Memory Control Unit (MCU): On-chip MCU and the L2 cache controller to reduce latency.

Chip Multithreading (CMT): Each core executes one thread, a different form of multi-threading compared to traditional implementations.

Multi-processing support: Snoop controller ensures cache coherency across multi-processor systems.

Theoretical peak performance: 2.4 Gflop/s at 1.2 GHz

Future scaling: Potential for frequency scaling in later stages of its lifecycle

Chip Layout and Design: The Memory Control Unit and L2 cache controller are integrated into the chip to minimize latency.

What Came After?

The Sun4v architecture, introduced with the UltraSPARC T1 and T2 processors, brought built-in hypervisor support (Logical Domains / LDOMs). This enabled efficient hardware-level virtualization, allowing multiple Solaris instances to run on a single server with superior thread scalability and power efficiency. But with time and evolving technology, this SPARC server too started losing its value.

Regarding UltraSPARC processors though, being considered a legacy system is the only option. It is used sparsely in some enterprises that have not modernized their hardware yet. UltraSPARC emulation remains viable for such companies.

The Future of Business Applications Running on SPARC

SPARC servers have their place in many organizations. Unfortunately, it’s not due to the uniqueness of the hardware anymore. Rather, it’s because they lack good alternatives for running their mission-critical Solaris applications.

These applications are vital to their business, powering day-to-day operations. But outdated hardware is causing serious issues:

• Downtime
• Business disruption
• Security breaches
• Higher maintenance costs
• Spare parts scarcity
• Diminishing pool of skilled professionals

This creates a situation that demands immediate action. Yet, businesses are either not prioritizing or don’t know where to start.

SPARC hardware emulation emerges as a risk-free, quick, and economical alternative here. If you’re looking for the leader in UltraSPARC emulation, Stromasys is the way to go.

Charon-SSP is Stromasys’ meticulously engineered SPARC emulator. It replicates the behavior of your current hardware and creates a similar environment on modern hardware, either on-premises or cloud.

As a result, your critical legacy applications run unmodified on modern platforms without rewriting, re-designing, or recertifying. The entire process is frictionless and can be completed within days to weeks.

While we understand UltraSPARC emulation is not the same as the original hardware, it matches the standards of work and performance expected from modern computers. You will be able to concentrate on innovation rather than the many problems of legacy infrastructure.